IEEE Journal of Solid-State Circuits · 2000 · 36 citations · 7 references
EngineeringElectrical EngineeringAnalog ElectronicsMicroelectronicsWireless CommunicationsCmos Circuit DesignLow-noise Circuit DesignMixed-signal Integrated Circuit DesignRadio-frequency Integrated CircuitsReceiver SystemsSignal ConditioningCmos Analog Integrated CircuitsCmos Radio-frequency CircuitsLinearityLow-pass FiltersMaximum GainNoise FigureSuperheterodyne ArchitectureSuperheterodyne Receivers
An intermediate-frequency (IF) baseband strip for a superheterodyne GSM receiver developed in a 0.25-/spl mu/m CMOS technology is presented. It contains a 71-MHz IF amplifier, programmable between -20 and +60 dB in 2-dB steps; a quadrature demodulator; and two low-pass output filters for channel selection. Measurements show an overall maximum gain of 89 dB and a noise figure of 3.8 dB. Phase and amplitude mismatches of the demodulator are below 10 and 0.1 dB, respectively. The high linearity required by the blocking and intermodulating signals, which are not completely suppressed by the IF filter, has been achieved using 4.7 mA from the 2,5-V power supply.
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