Attenuation compensation in distributed amplifier design

Abstract

A high-gain common-gate FET that presents at its drain a broadband impedance characterized by a (frequency-dependent) negative resistance and a capacitance is examined theoretically and experimentally. Loading the input and/or the output lines of a distributed amplifier with this circuit reduces the signal losses, leading to an increase in the allowed number of active devices with a consequent increase in the gain-bandwidth and gain-maximum-frequency products. The cascode circuit, a related loss reduction network, is also evaluated because of its use in distributed amplifiers. Several designs employing the common-gate FET loss-compensating circuit and/or the cascode amplifying circuit are compared to a conventional distributed amplifier optimized for gain-bandwidth product. Simulated gain-maximum-operating frequency product increases of 27% to 245% over that of the optimized conventional distributed amplifier are shown. The increase in single-stage amplifier gain provided by this technique often results in (proportionally) higher maximum output power.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>