Level-shifted and voltage-reduced 0.5 mu m BiCMOS circuits

Abstract

5-V BiCMOS digital circuits can provide significant speed improvement over CMOS circuits when driving heavy capacitance loads. The most commonly used 5-V BiCMOS circuit is the partial-swing circuit, which has 2-V/sub be/ reduction of its output swing. The V/sub be/ losses reduce both the noise margin and the overdrive voltage to the driven circuits. Owing to nonscaling of the bipolar V/sub be/, the effect becomes more severe as power supply is reduced. This partial-swing BiCMOS circuit has limited speed improvement over a 3.3-V conventional 0.5- mu m CMOS circuit when implemented in a scaled-down 0.5- mu m, 3.3-V BiCMOS technology. The concept of level-shifting a BiCMOS circuit is shown. The V/sub h/ and V/sub l/ supply rails for CMOS circuits are offset by V/sub be/ ( equivalent to 0.8 V) from the V/sub dd/ and V/sub ss/ supplies, respectively. After a V/sub be/ reduction similar to that in a partial-swing circuit, the output swing of the BiCMOS circuit matches the CMOS supply levels. Thus, CMOS-like noise margin and overdrive voltage can be achieved. The V/sub be/ shift can be implemented simply by an NPN transistor connected as a diode, or by more complex voltage-regulator circuitry. For a single 5-V V/sub dd/ supply and grounded V/sub ss/, the V/sub h/ and V/sub l/ for CMOS circuits are about 4.2 V and 0.8 V respectively. The net voltage across CMOS circuits is then (V/sub h/-V/sub l/), i.e. 3.4 V, which is close to a 3.3-V scaled-down supply for 0.5- mu m CMOS devices.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>