Analysis and Design of CMOS Received Signal Strength Indicator

Abstract

This paper presents a CMOS received signal strength indicator (RSSI) based on the successive detection architecture. Theoretical analyses of the RSSI value, error, and dynamic range are developed. The RSSI value relates to the single-stage voltage gain and the saturated output voltage level of each limiting ampifier cell. The RSSI error depends only on the single-stage voltage gain and the RSSI dynamic range is determined by both the single-stage voltage gain and the number of stages of a limiter. To confirm the derived equations of the RSSI error and dynamic range, a prototype RSSI and limiter circuit was fabricated. The measured total voltage gain of the implemented six-stage limiter is 60 dB, the bandwidth is 30 MHz and the input sensitivity is -61 dBV. The measured RSSI error is within ±1 dB over 55 dB of the RSSI dynamic range, which agrees well with the predicted values by the derived equations. The implemented RSSI and limiter circuit in a 0.18 μm CMOS process consumes 2.6 mA from a 1.8 V supply voltage.