IEEE Journal of Solid-State Circuits · 1989 · 12 citations · 1 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureMemorySystem-on-chip DesignCachingInstruction Set ArchitectureMemory HierarchyMemory Subsystem DesignMicroarchitecture DesignVirtual MemoryCache ArchitectureCache DesignCache ManagementContent-addressable MemoryContent-addressable Memory (Cam)High Bandwidth MemoryMemory BandwidthMemory Circuit Design
The design of a single chip (WE-32201) that includes both a content-addressable memory-based management unit and a large data/instruction cache is described. The chip belongs to AT&T's WE-32200 chip set and is fabricated using a 1 mu m twin tub CMOS process. It boosts the performance of the entire chip set significantly by providing high memory bandwidth and virtual-memory-management support. The combination of high-performance circuit design and system architectural design techniques makes the chip a major enhancement to the chip set.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
1