90-nm Process-Variation Adaptive Embedded SRAM Modules With Power-Line-Floating Write Technique

Abstract

The power consumption of a low-power system-on-a-chip (SoC) has a large impact on the battery life of mobile appliances. General SoCs have large on-chip SRAMs, which consume a large proportion of the whole LSI power. To achieve a low-power SoC, we have developed embedded SRAM modules, which use some low-power SRAM techniques. One technique involves expanding the write margin; another is a power-line-floating write technique, which enables low-voltage write operation. The power-line-floating write technique makes it possible to lower the minimum operating supply voltage by 100 mV. The other techniques involve using a process-variation-adaptive write replica circuit and reducing leakage current. These techniques reduce active power during write operations by 18% and reduce active leakage of the word-line driver by 64%. The prototype SRAM modules achieve 0.8-V operation, and a 512-kb SRAM module achieves 48.4-/spl mu/A active leakage and 7.8-/spl mu/A standby leakage with worst-leakage devices.