Stress effects of the inter-level dielectric layer on the ferroelectric performance of integrated SrBi2Ta2O9 capacitors

Abstract

The thermal stress effects of the inter-level dielectric (ILD) layer on the ferroelectric performance of integrated Pt/SrBi2Ta2O9(SBT)/Pt capacitors were investigated. Two different thin film materials, pure SiO2 grown at 650 °C and B- and P-doped SiO2 grown at 400 °C by chemical vapor deposition techniques, were tested as an ILD layer. The ILD layer encapsulated the SBT capacitor array. During high temperature thermal cycling (up to 800 °C) after ILD deposition, which is used for both densifying the ILD and curing of the various damage imposed on the SBT capacitors, a large thermal stress occurred in the bottom Pt layer due to the thermal expansion mismatch between the various layers. In particular, the pure SiO2 ILD layer between the capacitors did not allow thermal expansion of the Pt layers, which led to a large accumulation of compressive stress in the layer. This resulted in hillock formation in the bottom Pt layer and eventual capacitor failure. However, the B- and P-doped SiO2 ILD layer contracted during thermal cycling by removing residual impurities, which allowed greater expansion of the Pt layer. Therefore, compressive stress accumulation did not occur and excellent ferroelectric properties were thus obtained from the integrated capacitor array.