A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link

Abstract

A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30μm. The total layout area is 2mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 0.18μm CMOS and the chip thickness is 10μm. 4-phase TDMA reduces crosstalk and the BER is <10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">minus;12</sup> . Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver