2006 · 92 citations · 13 references
EngineeringComputer EngineeringElectrical EngineeringDigital CommunicationLow-power DesignMicroelectronicsClock Distribution NetworksClock ManagementHigh-frequency Semiconductor DevicesMicrowave Integrated CircuitsMixed-signal IntegrationRadio-frequency Integrated CircuitsCrosstalkCrosstalk CancellationCrosstalk Noise MitigationInductive CouplingNoise ImmunityRadio Frequency TransceiversTransceiver ArchitecturesTransceiver Design
A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30μm. The total layout area is 2mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 0.18μm CMOS and the chip thickness is 10μm. 4-phase TDMA reduces crosstalk and the BER is <10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">minus;12</sup> . Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver
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A 160Gb/s interface design configuration for multichip LSI
Takayuki Ezaki, Kazuhiro Kondo, Hiroshi Ozaki et al. · 2004 · 85 citations
Engineering, Computer Engineering, Electrical Engineering +17