EngineeringElectrical EngineeringCircuit TheoryMicroelectronicsSemiconductor DevicesCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyDevice ModelingIntegrated Circuit DesignMetal-oxide-semiconductor Field-effect TransistorsTransistor BiasingDifferential ResistanceLatch DesignLatchup Mitigation
A model is presented for the parasitic SCR in bulk CMOS. The model shows the exact way that the shunting resistances alter the terminal V-I characteristics. It describes a negative differential resistance (NDR) range which is the only requirement for latch-up if certain biasing conditions are met. The NDR region will start when the product of current and shunting resistance equals the built in voltage and will occur for a <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</inf> + a <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</inf> < 1 (or β <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</inf> β <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</inf> < 1). The conditions for the center junction to become forward biased are given. If these conditions are met, the SCR will latch-up. If these conditions are not met, latch-up becomes dependent on the biasing circuit.