Design of a high-speed Prolog machine (HPM)

Abstract

This paper describes a High-speed Prolog Machine (HIM) architecture and its hardware structure, which are developed as a product of Fifth Generation Computer System (FGCS} project in Japan. HIM realizes high performance and provides a practical programming environment. A major HIM feature is a large memory capacity and specialized hardware for unification and stack operations. HIM has a compiler-oriented architecture with high-level stack-control instructions. Furthermore, the HIM architecture provides side-effect operations, nonlocal-exit control and multiprocess support primitives, which are effective to develop system programs. The performance is estimated at 280 KLIPS (Kilo Logical Inferences Per Second) in executing a deterministic "concatenate" Prolog program. The HIM processor is implemented with high-speed CCML {Current Mode Logic) chips and with I00 nanosecond machine cycle.