Nanowire FETs for low power CMOS applications featuring novel gate-all-around single metal FUSI gates with dual Φ<inf>m</inf> and V<inf>T</inf> tune-ability

Abstract

A simple and cost-effective single metal gate scheme was successfully demonstrated to form gate-all-around (GAA) nanowire FETs with optimized dual V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> for low power CMOS applications. FUSI gate-induced stress effects were shown to be of great relevance to device performance. At an I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Off</sub> of 20 pA/mum, superior I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">On</sub> of 1180 and 405 muA/mum were obtained for NFETs and PFETs at a V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> of 1.2 V.