A time-domain architecture and design method of high speed A-to-D converters with standard cells

Masao Takayama, Shiro Dosho, Noriaki Takeda, Masaya Miyahara, Akira Matsuzawa

2011 · 10 citations · 2 references

Concepts

Abstract

In this paper, we describe a new method to deal with analog signal in time domain. The method converts voltage signal to time-interleaved phase modulation signal of clock edge. After being amplified by a new time amplifier(TA), phases of the signal are converted to digital codes by successive approximation time-to-digital converter(SA-TDC). The test chip includes 8 interleaved 4bit SA-TDCs with short latency. The chip operates up to 4.4GHz. The measured ENOB is 3.51bit and FOM is 0.49pJ/conv.

References

2