2005 · 34 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsVlsi DesignCmos Circuit DesignDigital Integrated Circuit DesignDigital Integrated CircuitsDynamic Power ReductionLow-power Digital Circuit DesignMixed-signal Integrated Circuit DesignAsynchronous Circuit DesignAsynchronous Digital Circuit DesignBinary SearchClock Network Power ReductionPower ConsumptionPower Consumption Optimization
Using binary-weighted differential-delay cells and an asynchronous binary search circuit, the proposed 1.0V 0.25 /spl mu/m all-digital DLL achieves nearly 2 orders of magnitude reduction in power consumption, a 36% reduction in jitter, and a 33% reduction in locking cycles, compared to conventional fast-lock mixed-mode DLL.
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