2001 · 345 citations · 22 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureEmbedded SystemsLow-power DesignDynamic Power ReductionEnergy-efficient Embedded SystemsPower ManagementPower OptimizationPower-aware DesignVoltage ScalingDynamic Voltage And Frequency ScalingLow-power MicroarchitecturePower ConsumptionPower Consumption OptimizationPower Management TechniquesScheduler DesignVoltage Scaling In MicroprocessorsWearable Devices
Power consumption limits wearable devices, and interactive applications generate bursty workloads that require matching performance, so voltage scaling is used to reduce power at low speeds. The paper aims to present a system that dynamically adjusts a microprocessor’s frequency and voltage to match workload demands. The system accomplishes this by enabling frequency and voltage scaling of the microprocessor. Measurements show that energy per instruction at minimal speed is one‑fifth of that at full speed, scaling can be performed in 140 µs, and a power‑aware H.263 decoder outperforms static and interval‑based schedulers.
Power consumption is the limiting factor for the functionality of future wearable devices. Since interactive applications like wireless information access generate bursts of activities, it is important to match the performance of the wearable device accordingly. This paper describes a system with a microprocessor whose speed can be varied (frequency scaling) as well as its supply voltage. Voltage scaling is important for reducing power consumption to very low values when operating at low speeds. Measurements show that the energy per instruction at minimal speed is 1/5 of the energy required at full speed. The frequency and voltage can be scaled dynamically from user space in only 140 μs. This allows power-aware applications to quickly adjust the performance level of the processor whenever the workload changes. Experiments with an H.263 video benchmark show that the power-aware decoder outperforms a static fixed-frequency policy as well as a dynamic interval-based scheduler.
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Scheduling for Reduced CPU Energy
1994 · 1.1K citations
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