IEEE Computer Architecture Letters · 2007 · 59 citations · 31 references
ComputingComputer EngineeringComputer ScienceComputer NetworksInterconnection NetworksSystem-on-chip DesignCache CoherenceCircuit SwitchingLatency OptimizationMulticore Processor DesignProcessor Core DesignSwitching TechniquesCircuit Switched NetworksCircuit Switching ProtocolsInterconnect DelayLow-latency CommunicationLow-latency DesignOn-chip CommunicationOn-chip InterconnectsPerformance Analysis Of Circuit Switching
Circuit-switched networks can significantly lower the communication latency between processor cores, when compared to packet-switched networks, since once circuits are set up, communication latency approaches pure interconnect delay. However, if circuits are not frequently reused, the long set up time and poorer interconnect utilization can hurt overall performance. To combat this problem, we propose a hybrid router design which intermingles packet-switched flits with circuit-switched flits. Additionally, we co-design a prediction-based coherence protocol that leverages the existence of circuits to optimize pair-wise sharing between cores. The protocol allows pair-wise sharers to communicate directly with each other via circuits and drives up circuit reuse. Circuit-switched coherence provides overall system performance improvements of up to 17% with an average improvement of 10% and reduces network latency by up to 30%.
31
Steven Cameron Woo, Moriyoshi Ohara, Evan Torrie et al. · 1995 · 3.6K citations · Full text
James Laudon, Daniel Lenoski · 1997 · 779 citations · Full text
Orion: a power-performance simulator for interconnection networks
Hangsheng Wang, Xinping Zhu, Li-Shiuan Peh et al. · 2002 · 681 citations
Orion: a power-performance simulator for interconnection networks
Hangsheng Wang, Xinping Zhu, Li-Shiuan Peh et al. · 2003 · 340 citations