ISIS: a system for performance driven resource sharing

Abstract

The authors establish the importance of accurate bit-level area and delay modeling to the quality of circuits synthesized by resource sharing systems. They show that bit-level accuracy and integration with logic optimization are both desirable and feasible, since the added execution time is a small fraction of the total optimization time. The implementation of a resource sharing system called ISIS, which uses bit-level modeling, accounts for control delays, and optimizes sharing and resource performance selection together to generate high-quality circuits from register transfer language (RTL) descriptions, is described. >