High-level power modeling, estimation, and optimization

TLDR

Power has become a design constraint on par with area, performance, and testability, driven by the demand for high‑speed, low‑power personal computing and wireless devices, rising packaging and cooling costs, and stricter reliability requirements that necessitate automatic low‑power VLSI design tools. The paper surveys recent literature on power modeling, estimation, synthesis, and optimization techniques for early design stages. The survey examines representative contributions in this area that have appeared in the recent literature.

Abstract

Silicon area, performance, and testability have been, so far, the major design constraints to be met during the development of digital very-large-scale-integration (VLSI) systems. In recent years, however, things have changed; increasingly, power has been given weight comparable to the other design parameters. This is primarily due to the remarkable success of personal computing devices and wireless communication systems, which demand high-speed computations with low power consumption. In addition, there exists a strong pressure for manufacturers of high-end products to keep power under control, due to the increased costs of packaging and cooling this type of device. Last, the need of ensuring high circuit reliability has turned out to be more stringent. The availability of tools for the automatic design of low-power VLSI systems has thus become necessary. More specifically, following a natural trend, the interests of the researchers have lately shifted to the investigation of power modeling, estimation, synthesis, and optimization techniques that account for power dissipation during the early stages of the design flow. This paper surveys representative contributions to this area that have appeared in the recent literature.