Design of a sampling strategy for measuring and compensating for overlay errors in semiconductor manufacturing

Abstract

To enhance the resolution and alignment accuracy in semiconductor manufacturing, it is important to measure overlay errors and control them into the tolerances by removing assignable causes. A number of related studies have been done to examine the factors causing the overlay errors, to propose mathematical models and to develop overlay error control methods. However, the involved sampling strategies received little attention. This study aimed to propose specific designs of sampling patterns effectively to measure and compensate for overlay errors within the limited number of samples in practice. To verify the validity of the proposed approach, the sampling strategies were compared using empirical data from a wafer fabrication facility. The proposed sampling patterns had a higher goodness of fit for the overlay model and lower residuals after compensation. This paper concludes with our findings and discussions on further research.