40-Entry unified out-of-order scheduler and integer execution unit for the AMD Bulldozer x86–64 core

Abstract

AMD's two-core Bulldozer module implements the AMD x86-64 micro architecture in an 11-layer 32-nm SOI HKMG technology. The 40-instruction out of-order unified integer scheduler issues up to four operations per cycle and supports single-cycle wake-up of dependent operations. The 2.37mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> integer execution unit supports single-cycle data bypass among four independent func tional units. Compared to previous AMD x86-64 cores, project goals reduce the number of F04 inverter delays per cycle by more than 20%, while maintaining constant IPC, to achieve higher frequency and performance in the same power envelope, even with increased core counts.