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63 ps ECL circuits using advanced SICOS technology
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1986
Year
Unknown Venue
Electrical EngineeringEngineeringShallow ProfilePower DeviceNanoelectronicsElectronic EngineeringPower Semiconductor DevicePs Ecl CircuitsPower ElectronicsMinimum Gate DelayMicroelectronicsSemiconductor DeviceAdvanced Sicos Technology
A high speed silicon bipolar transistor structure and very high speed ECL circuits are demonstrated. The circuits were fabricated with an advanced SICOS technology featuring emitter shallow profile and very shallow graft base regions. Minimum gate delay of 63 ps/G at FI=1 and 79 ps/G at FI=3 were obtained with advanced SICOS technology.