CMOS ternary flip-flops and their applications

Abstract

We demonstrate a procedure for designing CMOS ternary circuits based on a discussion of threshold comparison, transmission, and union operations. Using some basic CMOS ternary circuits, we design CMOS ternary flip-flops (tri-flops) such as ternary latch and various master/slave triflops. These tri-flops have two additional binary inverse outputs with a fixed threshold. As examples of sequential circuit design using these triflops, we present a modulo-9 up-counter and a mixed valued counter.