IEE Proceedings E Computers and Digital Techniques · 1988 · 16 citations · 0 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureMicroelectronicsSemiconductor DevicesCmos Circuit DesignCombinational Logic DescriptionDigital Integrated Circuit DesignDigital Integrated CircuitsDigital Logic DesignLogic SynthesisCmos Logic CircuitsCmos Logic DesignFlip-flop ArchitectureFlip-flop DesignFlip-flopsSequential Circuit SynthesisSequential DesignSequential Logic Design
We demonstrate a procedure for designing CMOS ternary circuits based on a discussion of threshold comparison, transmission, and union operations. Using some basic CMOS ternary circuits, we design CMOS ternary flip-flops (tri-flops) such as ternary latch and various master/slave triflops. These tri-flops have two additional binary inverse outputs with a fixed threshold. As examples of sequential circuit design using these triflops, we present a modulo-9 up-counter and a mixed valued counter.