An Embedded 65 nm CMOS Baseband IQ 48 MHz–1 GHz Dual Tuner for DOCSIS 3.0

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8<formula formulatype="inline"><tex Notation="TeX">$~$</tex></formula>MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all the stringent SCTE 40 specifications over the 48–1004<formula formulatype="inline"><tex Notation="TeX">$~$</tex> </formula>MHz bandwidth, without using any external components or SAW filters. Enabling technologies are a harmonic rejection front-end, a low-noise high-frequency resolution phase-locked loop (PLL) and digital image rejection. To our knowledge this is the first reported multi-channel Broadband Tuner embedded in a DOCSIS<formula formulatype="inline"><tex Notation="TeX">$~$</tex></formula>3.0 System on a Chip implemented in a 65 nm pure digital CMOS technology. </para>