V-Band High Data-Rate I/Q Modulator and Demodulator With a Power-Locked Loop LO Source in 0.15-/spl mu/m GaAs pHEMT Technology

Abstract

A wideband sub-harmonically pumped (SHP) modulator and demodulator fabricated in 0.15-μm GaAs pseudomorphic high electron-mobility transistor technology are demonstrated in this paper. The chip is appropriate for emerging 60-GHz multi-gigabit communication applications. Digital modulation degradation resulting from in-phase/quadrature mismatch is effectively minimized by the proposed power-locked loop system. By overcoming the bandwidth limitations and quadrature errors in amplitude and phase, the sideband suppression ratio exhibits broadband performance with the feedback mechanism. By using the SHP mixer structure, the dc offset problem is mitigated because of decreased 2× local oscillator leakage. In addition, sub-circuit design considerations and feedback stability are described in this paper. The SHP modulator and demodulator demonstrate flat conversion-gain responses of -14 ±2 dB and -14 ±1 dB, respectively, from 51 to 68 GHz. Properties of multi-gigahertz modulation and demodulation bandwidths show the potentials for gigabit applications. The amplitude and phase imbalances are restricted within 0.3 dB and 5° (±2.5°), respectively, regardless of modulation or demodulation. High data-rate digital modulation and demodulation are successfully performed through 16-QAM and 64-QAM schemes within four channels of the IEEE 802.15.3c standard with outstanding error vector magnitude performances.