Fault-test analysis techniques based on logic simulation

Abstract

In Part I of this paper we describe FANSSIM, a logic simulator whose primary use is fault analysis, i.e., fault test verification. The main feature of FANSSIM, aside from precise timing simulation, is high-speed/low-cost performance. The performance achieved ranges from 10,000 to 80,000 signals per dollar for typical simulations. Techniques contributing to this performance are: exclusive simulation of activity; a table-driven method for individual element simulation; an event-scheduling mechanism which remains economical for large, active networks; a three-state simulation method operating at high speed for 0-1 and 1-0 signals; and implementation of the central simulator subroutine in 360-Assembly Language. Additional FANSSIM capabilities not generally available in other simulators are the capability to define and use a large variety of nonprimitive logic elements without sacrificing speed or space, an oscillation-safe technique for network initialization, dynamic and accumulated activity reporting in terms of element transitions, and the transmission of nonbinary messages through a logic network.