Applied Physics Letters · 2014 · 18 citations · 18 references
EngineeringElectrical EngineeringMaterials EngineeringMicroelectronicsSemiconductor DevicesSemiconductor MaterialsCarrier TransportDevice CharacterizationDevice SimulationField-effect TransistorsSemiconductor HeterostructuresWide Band Gap SemiconductorsHeterostructure Field-effect TransistorsHeterostructure TransistorsQuantum Tunneling EffectsThreshold VoltageThreshold Voltage ModelingTrap FillingTrap KineticsTrapping Effects
A measurement methodology involving the synchronous switching of gate to source voltage and drain to source voltage (VDS) was proposed for determining the shift of threshold voltage after an AlGaN/GaN heterostructure transistor endures high VDS off-state stress. The measurement results indicated slow electron detrapping behavior. The trap level was determined as (EC – 0.6 eV). Simulation tool was used to analyze the measurement results. The simulation results were consistent with the experimental results; and a relationship between the buffer trap and threshold voltage shift over time was observed.
18
Davide Bisi, Matteo Meneghini, Carlo De Santi et al. · IEEE Transactions on Electron Devices · 2013 · 443 citations · Full text
Chihoko Mizue, Yujin Hori, Marcin Miczek et al. · Japanese Journal of Applied Physics · 2011 · 243 citations