Two-Gate Transistor for the Study of Si/SiO₂ Interface in Silicon-on-Insulator Nano-Channel and Nanocrystalline Si Memory Device

Abstract

A two-gate single electron memory device with active area of 1.5×10 -10 cm 2 allows the study of Si/SiO 2 interface in nano-scale channels of silicon on insulator (SOI) and nanocrystalline Si (nc-Si) dots. The basis of this device is a trench (150–600 nm wide) defined inside a large “inversion” gate electrode into which nc-Si (8±1 nm diameter) can be deposited by remote plasma enhanced chemical vapor deposition. Device structure is analyzed with 2-D and 3-D numerical simulation of Poisson's and continuity equations, which show uniform surface potential of channel. The device design allows for tuning of threshold shifts as well as controlling the length of active area from 65–165nm with applied gate bias. This allows for quantifiable threshold shifts for charged interface defects on the channel as well as charge stored in nc-Si. Threshhold shifts of between 70–120 mV are calculated depending on the location of charged species along the width of the 30nm wide channel. To study energy levels of single defect sites, lifetime studies of charged sites are possible with and without deposited nc-Si.