Growth of two-dimensional arrays of silicon nanocrystals in thin SiO₂layers by low pressure chemical vapour deposition and high temperature annealing/oxidation. Investigation of their charging properties

Abstract

Two-dimensional arrays of silicon nanocrystals embedded in ultrathin SiO2 layers for application in silicon nanocrystal memories were fabricated by a three-step process: (a) growth of a tunnelling silicon oxide, (b) low pressure chemical vapour deposition (LPCVD) of a thin layer of amorphous silicon (α-Si), and (c) solid phase crystallization of the α-Si layer in a high temperature furnace under nitrogen flow, followed by thermal oxidation in the same furnace. Transmission electron microscopy (TEM) was used for the structural characterization of the three-layer structure and the determination of layer thicknesses and silicon nanocrystal size, while capacitance–voltage (C–V) and current–voltage (I–V) measurements were used to investigate the charging properties of the silicon nanocrystal layer. In an attempt to increase the silicon nanocrystal density, as suggested in the literature, a dip of the oxidized wafer in diluted HF before LPCVD deposition was used, but this step was found to seriously affect the charging properties of the structure.