Compact parallel optical modified-signed-digit arithmetic-logic array processor with electron-trapping device

Guoqiang Li, Feng Qian, Hao Ruan, Liren Liu

Applied Optics · 1999 · 38 citations · 29 references

Concepts

Abstract

A compact two-step modified-signed-digit arithmetic-logic array processor is proposed. When the reference digits are programmed, both addition and subtraction can be performed by the same binary logic operations regardless of the sign of the input digits. The optical implementation and experimental demonstration with an electron-trapping device are shown. Each digit is encoded by a single pixel, and no polarization is included. Any combinational logic can be easily performed without optoelectronic and electro-optic conversions of the intermediate results. The system is compact, general purpose, simple to align, and has a high signal-to-noise ratio.

References

29