A composite varactor for simultaneous high power and high efficiency harmonic generation

Abstract

The proposal of connecting several varactor wafers in series to obtain higher breakdown voltages without loss of cutoff frequency is explored theoretically and experimentally. Calculations indicate that for a common wafer and junction geometry, the cutoff frequency of series-stacked varactors will vary approximately as V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</inf> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1/2</sup> instead of the more rapid V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</inf> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> or V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</inf> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3/2</sup> variation characteristic of a single wafer. The virtue of this scheme has been demonstrated in a 4-to-12 Gc/s multiplier using varactors consisting of 1, 2, 3, and 4 series-connected, epitaxial GaAs, surface barrier wafers. As anticipated, the varactor breakdown voltages increased directly with the number of wafers employed and the power capability as the square of that number, while efficiency decreased only slightly. A maximum power output of 1.2 watts at 12 Gc/s was obtained with 62 percent efficiency in a tripler circuit.