Automatic Test Generation From Semi-formal Specifications for Functional Verification of System-on-Chip Designs

Abstract

In common design flows of system-on-chip (SoC) designs functional verification requires 70% of the entire design effort. Most of the effort for functional verification is spent on finding and creating adequate testcases to verify that the modeled design corresponds to its specification. This is done manually, since automatic test case generation from the specification is often not possible due to the informal, non-machine readable structure of the specification document. Formal specification languages would ease the parsing process, however, these formats are difficult to use by system engineers from different domains. A promising trade-off are semi-formal specification formats, which are both easy-to-parse and easy-to-use. The SIMBA project focuses on semi-formal use case-based specification formats, which are used to automatically generate a transaction-based SystemC verification platform. Finally, these SystemC testcases are simulated together with the System-under- Verification (SuV) to verify that it fulfills the given specification. This results in a novel design methodology regarding requirements elicitation and automatic test case generation. A demonstration is given by applying this methodology to a SystemC RFID controller model. It is shown that the demonstrated approach automates and improves the functional verification of SoCs.