Capacitance modelling for double-sided Si detectors with double-metal readout

Abstract

A model is presented for calculation of the large contribution to electronic noise coming from the new double-metal readout on double-sided silicon strip detectors. It applies to the two types of N-side insulating schemes: electrode extension or P-barrier. The 3D capacitor structure is described by a grid model, whose sub-elements are all 2D calculated, using analytic formulae, discrete electrostatics and device simulation (PROUDS, TOSCA). The model is tested on existing detectors (SI, HPK, CSEM). All calculations are static.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>