Design considerations for fully depleted SOI transistors in the 25–50 nm gate length regime - Concepedia

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Design considerations for fully depleted SOI transistors in the 25–50 nm gate length regime

16

Citations

13

References

2003

Year

R.J. Luyken, T. Schulz, J. Hartwich, L. Dreeskornfeld, M. Städele, W. Rösner

Solid-State Electronics

Electrical EngineeringEngineeringElectronic EngineeringSoi TransistorsApplied PhysicsDesign ConsiderationsMicroelectronicsSemiconductor Device

References

	Year	Citations

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