Evolution, challenge, and outlook of TSV, 3D IC integration and 3d silicon integration

TLDR

3D integration comprises 3D IC packaging, 3D IC integration, and 3D Si integration, with TSV distinguishing the latter two from packaging, which does not use TSV. The study investigates TSV as the core of 3D IC/Si integrations and proposes generic, low‑cost, thermal‑enhanced SiPs employing passive TSV interposers. The authors propose generic, low‑cost, thermal‑enhanced SiPs employing various passive TSV interposers. The paper presents the origin of 3D integration and discusses its evolution, challenges, outlook, and road maps.

Abstract

3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They are different and in general the TSV (through-silicon via) separates 3D IC packaging from 3D IC/Si integrations since the latter two use TSV but 3D IC packaging does not. TSV (with a new concept that every chip or interposer could have two surfaces with circuits) is the heart of 3D IC/Si integrations and is the focus of this investigation. The origin of 3D integration is presented. Also, the evolution, challenges, and outlook of 3D IC/Si integrations are discussed as well as their road maps are presented. Finally, a few generic, low-cost, and thermal-enhanced 3D IC integration system-in-packages (SiPs) with various passive TSV interposers are proposed.