Capacitor test simulation of retention and imprint characteristics for ferroelectric memory operation

Abstract

Abstract Ferroelectric memory devices are subject to failure due to both a simple loss of retention or due to imprint. The difference between retention and imprint as described here depends on the test history of the device. A pulsed capacitor test has been devised to simulate the signal available to a typical memory cell after time and temperature stress. The test sequence consists of individual pulses used to compare the switched component to the non-switched component with the difference being the signal available for memory operation. It has been found that this signal when plotted versus log time for a fixed bake temperature stress produces a straight line.