A 20-ps Si bipolar IC using advanced super self-aligned process technology with collector ion implantation

Abstract

A super self-aligned process technology, SST-1B, which is an advanced version of the previously proposed SST-1A in high-speed Si bipolar LSIs is discussed. A selectively ion-implanted collector (SIC) process and bird's-beak-free isolation process are utilized. The SIC process is designed to improve shallow base-collector profiles in the intrinsic region. It reduces base width and intrinsic base resistance, and suppresses the base push-out effect (Kirk's effect) in high-current operations. The SIC profile is easily controlled by 150-200 keV phosphorous ion implantation at the base-collector junction. Using these processes, SST-1B has achieved a high cutoff frequency of 21.1 to 25.7 GHz and a fast switching delay of 20.5 ps/G for nonthreshold logic and 34.1 ps/G for emitter-coupled logic. SST-1B has potential applications to 50-ps/G logic LSIs and 10-GHz SSIs. Device simulation indicates that it is possible to achieve a cutoff frequency of 40-50 GHz in a future scaled-down Si bipolar transistor with a 40-nm base and graded collector.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>