Hardening Techniques for MRAM-Based Nonvolatile Latches and Logic

TLDR

MRAM, a fast, CMOS‑compatible, radiation‑hard nonvolatile memory storing data in electron spin, is attractive for aerospace and avionic electronics but its peripheral CMOS circuits make nonvolatile latches and logic vulnerable to single‑event effects. The paper proposes hardening techniques to mitigate single‑event effects in MRAM‑based nonvolatile latches and logic. The authors present a rad‑hard MRAM latch design and apply a TMR technique to configurable logic blocks to suppress single‑event transients on data paths. Hybrid simulations using a 65 nm design kit and an MRAM compact model demonstrate the radiation hardness and performance of the proposed hardening methods.

Abstract

Magnetic RAM (MRAM) is considered as a promising nonvolatile memory technology for aerospace and avionic electronics thanks to its intrinsic hardness to radiation. Data is stored on the spin direction “up” and “down” of electrons instead of positive and negative charge. Thanks to its fast speed, easy integration with CMOS and infinite endurance, MRAM has been proposed to build up nonvolatile latches and logic circuits to overcome the power challenge of conventional CMOS circuits. However, they are vulnerable to single event effects (SEE) due to their CMOS peripheral circuits. Hardening techniques to mitigate SEE are described in this paper. A new design of Radhard MRAM latch is firstly presented. TMR technique is then implemented on configurable logic block (CLB) to mitigate SET on data paths. By using 65 nm design kit and an MRAM compact model, hybrid simulations have been done to demonstrate the radiation hardness and performance.