Mixed Digital–Analog Associative Memory Enabling Fully-Parallel Nearest Euclidean Distance Search

Abstract

In this paper, an associative memory architecture with mixed digital–analog search circuitry is proposed, which enables a fully-parallel nearest match-data search based on the Euclidean distance between input pattern and stored reference patterns. A test chip, implementing the proposed architecture, was designed in 0.35 µm complementary metal–oxide–semiconductor (CMOS) technology with two-poly and three-metal layers. The nearest-match unit consumes only 0.64 mm2 (12.5% of the total design area), while the whole chip area is 5.12 mm2. The layout-based simulated winner-search time, the time to determine the best-matching reference-data word for an input-data word among a database of 64 reference patterns (5-bit, 16 units), is lower than 160 ns. This corresponds to a performance requirement of 27 giga operations per second (GOPS)/mm2, if a general purpose computer with the same chip area would have to run the same workload. Furthermore, the power dissipation of the designed test chip is only about 38 mW/mm2 at this high processing performance.