Application of coreless substrate to package on package architectures

Abstract

The high performance application processors found in today's hand held wireless and mobile computing products, such as smart phones and tablet computers, require packages that can support demanding device performance and dense form factor requirements. The package architecture must enable the required signal routing, signal integrity, power delivery, physical form factor, manufacturability and cost. This paper reviews the approach taken to design and implement a package on package (PoP) that enables the integration of a 32nm silicon node processor with dual channel LPDDR memory in a compact 12×12 mm, 0.4 mm BGA pitch solution. The coreless substrate package technology used in this design allows the routing of signals from a 150 um silicon bump pitch array, while achieving a 0.7 mm bottom package z-height. Selection of the PoP interconnect scheme, signal routing approach, surface mount and reliability performance are addressed.