2.8 to 67.2mW Low-Power and Power-Aware H.264 Encoder for Mobile Applications

Abstract

A 2.8 to 67.2mW H.264 encoder is implemented on a 12.8mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die with 0.18μm CMOS technology. The proposed parallel architectures along with fast algorithms and data reuse schemes enable 77.9% power savings. The power awareness is provided through a flexible system hierarchy that supports content-aware algorithms and module-wise gated clock.