A 40GS/s 6b ADC in 65nm CMOS

Abstract

A 6b 65nm CMOS ADC exceeds the 29GS/S requirement of a 58Gb/s DP-QPSK optical receiver while operating up to 40GS/S. An inter-leaved architecture combines 16 SAR converters and an array of T/Hs with delay, gain, and offset calibration. A 1V 40mW 2.5GS/S subADC results in a total power of 1.5W, ENOB of 4.5b (3.9b) up to 10GHz (18GHz). An on-chip signal synthesizer simplifies production testing.