Process and design for ESD robustness in deep submicron CMOS technology

Abstract

The impact of drain process variation and physical layout design on the nMOSFET ESD performance of a 0.35 micron CMOS technology was investigated. It was found that the second breakdown current (It2) increases with arsenic nLDD and boron halo implant doses and decreases with increasing GBLDD phosphorus implant energy. Increasing the number of source/drain contacts and increasing the drain contact-to-gate spacing (drain CGS) while decreasing source CGS was shown to increase the value of It2. Testing of multiple finger structures showed only half of the fingers conducting during ESD pulses. This study suggests that this could be due to shared drain contacts in the multiple finger configuration.