A W-Band High-Efficiency CMOS Differential Current-Reused Frequency Doubler

Abstract

A W-band differential frequency doubler using a current-reuse configuration in a 65 nm CMOS process is presented in this letter. The differential current-reuse circuit with a second harmonic coupling transformer is introduced to improve conversion gain at small input powers minimizing the effect of the RF bypass capacitor. The proposed circuit achieves a conversion gain of 0.8 ~ -4.2 dB and a fundamental rejection above 19 dB in the input frequency range of 36.5~44 GHz with -4 dBm input power. It has conversion gain variation below 1 dB when the input power varies from -7.4 to 0.1 dBm at 77 GHz. The dc power consumption is 14 mW. It has the highest conversion gain with the smallest chip size of 0.22 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> among all V-/W-band CMOS frequency doublers.