A power amplifier with minimal efficiency degradation under back-off

Abstract

A zero voltage switching technique that can maintain its peak efficiency over a 12dB dynamic range of output power is presented. The application of the technique is illustrated by the design and simulation based verification of an 800 MHz, 130nm CMOS PA that achieves close to a constant drain efficiency of about 40% over a 12 dB dynamic range of output power. System level simulations show that the PA achieves an ACPR of -54dBc at 400 KHz and -60dBc at 600 KHz frequency offsets respectively.