Optimization of n- and p-type TFETs Integrated on the Same ${\rm InAs}/{\rm Al}_{x}{\rm Ga}_{1-x}{\rm Sb}$ Technology Platform

Abstract

Design of a suitable technology platform is carried out in this paper for co-integration of simultaneously optimized n- and p-type tunnel field-effect transistors (TFETs). InAs/Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Sb heterostructures are considered, and a 3-D full-quantum simulation approach is adopted to investigate the combined effect of Al mole fraction x and transverse quantization on band lineups at the heterojunction. Design optimization leads to a TFET pair with similar dimensions and feasible aspect ratios realized on the same InAs/Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.05</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.95</sub> Sb platform. These devices exhibit average subthreshold slopes below 60 mV/dec and relatively high ON-currents of 270 (n-TFET) and 120 μA/μm (p-TFET) at a low-supply voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> =0.4 V. Combined ON- and OFF-state performance of the proposed technology platform is expected to be compatible with low operating power applications, while potential candidates for low standby power scenarios are obtained by reducing TFET cross sections from 10 to 7 nm.