IEEE Transactions on Nuclear Science · 1983 · 11 citations · 0 references
EngineeringComputer EngineeringComputer ScienceEmbedded SystemsHardware-software Co-designInterconnection NetworksInterconnect ArchitectureInterconnect DesignBandwidthBlock TransferHardware-software Interface DesignHigh-speed InterconnectsHigh-speed Interface DesignSoftware Interface Design
A list processing microprocessor controlled host interface for FASTBUS has been constructed by connection of a FASTBUS cable segment to the VAX DR-32 Device Interconnect (DDI) implemented via the DEC DR-780 channel on a VAX-11/780 system. Block transfer rates of 5.7 megabytes/second (700 ns per 32 bit longword) are achieved on VAX-11/780 systems equipped with a single MS-780 memory controller, while interleaved dual memory controller systems reach 8.0 megabytes/second (500 ns per longword) performance. The hardware and software interface should work equally well on DR-750 equipped VAX-11/750 systems (with appropriate reductions in achievable bandwidth) as well as on any future VAX systems equipped with a DDI adapter.