Modeling and Simulation of LDO Voltage Regulator Susceptibility to Conducted EMI

TLDR

This paper presents a methodology dedicated to modeling and simulation of low‑dropout (LDO) voltage regulator susceptibility to conducted electromagnetic interference (EMI). The authors designed a test chip with a simple LDO structure and developed a transistor‑level model, validated by functional tests, Z‑parameter characterization, and direct power injection measurements, to predict LDO immunity and analyze the impact of subcircuits and parasitic elements. DPI measurement results show a good fit with model prediction up to 1 GHz.

Abstract

This paper presents a methodology dedicated to modeling and simulation of low-dropout (LDO) voltage regulator susceptibility to conducted electromagnetic interference (EMI). A test chip with a simple LDO structure was designed for EMC test and analysis. A transistor-level model, validated by functional tests, Z-parameter characterization and direct power injection (DPI) measurements, is used to predict the immunity of the LDO regulator. Different levels of model extraction reveal the weight contributions of subcircuits and parasitic elements on immunity issues. The DPI measurement results show a good fit with model prediction up to 1 GHz.