Electrical properties of silicon-implanted furnace-annealed silicon-on-sapphire devices

Abstract

The crystalline quality of s.o.s. layers can be improved near the silicon-sapphire interface by silicon implantation followed by recrystallisation. Device performance on such layers is markedly improved as to n-channel m.o.s.t. noise and leakage current, reverse diode current and lateral bipolar transistor gain. Minority-carrier lifetimes up to 50 ns are deduced.