A high-speed monolithic InP MISFET integrated logic inverter

Abstract

High dynamic range monolithic n-channel InP MISFET integrated inverter circuits with delay times of 350 ps have been fabricated on Fe-doped semi-insulating substrates using ion implantation for channel and contact regions and pyrolytic SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> for the gate insulation. These circuits, consisting of two active elements, a 4-µm channel-length normally-off enhancement driver MISFET, and a 4-µm gate-length normally-on depletion load MISFET are designed for use in direct-coupled high-speed logic. In comparison to the dominant GaAs MESFET approach, the present circuit does not require level shifting and uses only a single power supply. With <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_{DD} = 12.4</tex> V these inverters exhibit logic swings of 11.2 V, noise margins of 4.5 and 3.2 V, and dc gain in the linear region of 3.1.