A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO

Abstract

A 2.8Gb/s all-digital CDR uses a 10b glitch-free DCO which provides a 0.2 to 0.3% frequency tuning step to reduce the quantization effect. The CDR achieves 7.2ps <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> jitter at 2.5Gb/s and it operates from a 0.9 to 1.2V supply. The circuit occupies 300 times 430mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in a 0.13mum CMOS process and dissipates 13.2mW from a 1.2V supply when operating at 2.5Gb/s.