2014 · 16 citations · 6 references
EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignDigital Signal ProcessingLow-noise Circuit DesignNoise In Analog CircuitsSubthreshold Circuit DesignAnalog-to-digital Converter DesignCmos Analog Integrated CircuitsDistortion ReductionNonlinearitySubthreshold Analog Circuit DesignSubthreshold Inverter DesignSupply Voltage OptimizationVoltage
This paper presents a high-resolution ΔΣ modulator which is capable of operation under supply voltage as low as 250mV. A novel subthreshold inverter-based OTA is proposed and exploited in the switched-capacitor (SC) integrators, permitting a satisfied noise-shaping performance in the 4 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> -order feed-forward topology. With each stage's coefficient optimized, the integrators' internal swings and the distortion power stemming from OTAs' gain nonlinearity are minimized. Implemented in a 0.13μm CMOS with an OSR of 64 and a sampling frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> ) of 1.28MHz, this design achieves a measured DR of 77.0dB, SNDR of 73.3dB, and SFDR of 85.0dB over a 10kHz bandwidth. To the best of authors' knowledge, it appears to be the converter with highest SNDR observed among sub -0.5V designs.
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11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS
Hung-Yen Tai, Yao-Sheng Hu, Hung‐Wei Chen et al. · 2014 · 222 citations
Engineering, Computer Engineering, Electrical Engineering +17